The present invention relates to a novel split gate flash memory with improved erase operations and the method of making the same. More specifically, the present invention relates to a method for making improved split gate flash memory which utilizes the poly1 to poly2 Fowler-Nordheim channeling of charges through the sharp corner at the floating gate edge to achieve charge erase operation, and the improved split gate flash memory cells made therefrom. The present invention prevents or at least minimizes potential degradations in erase efficiency due to charge trapping as a result of oxide defects which exist at the sharp corner at the edges of the floating gate. The present invention also allows the size of the floating gate, thus the overall memory cell dimension, to be smaller than that typically achievable from the underlying photolithography technology. By doing so, the present invention allows scaling-down of the flash memory cells without incurring large expenses typically associated with equipment and/or process upgrade.
Flash memories are high-density nonvolatile semiconductor memories offering fast access times. Compared to other nonvolatile semiconductor memories such as conventional EEPROMs or EEPROMs, flash memories are most suitable for applications wherein there are expected frequent write and read operations. Because of its light weight compared to magnetic memories such as hard disk or floppy disk memories, flash memory has a tremendous potential in the consumer electronics market. With the rapid growth of digital cameras and the desire for light-weight notebook PCs, the demand for even higher density flash memories is ever increasing.
FIG. 1A shows a top view cell layout of a typical flash memory, and FIGS. 1B and 1C are illustrative schematic diagrams of the flash memory cell along lines B-Bxe2x80x2 and C-Cxe2x80x2, respectively. The flash memory cell contains a semiconductor substrate 1, which typically is a P-type silicon substrate with a doping level ranging from 5 to ohm-cm. Within the substrate 1, there are source region 2, typically an N-doped silicon, a drain region 3, also an N-doped silicon, and a channel region 4 between the source region 2 and the drain region 3. A tunnel oxide layer 5 is disposed over the channel region and the source and drain regions. Disposed over the tunnel oxide layer are one or more floating gate (poly-1), which, as shown in FIG. 1C, is positioned over a portion of the source region 2 and over a portion of the channel region 4. An insulating layer 6, which can be silicon dioxide, silicon nitride, or silicon oxynitride, is disposed covering the floating gate. A control gate is then disposed which covers a portion of the floating gate and a portion of the channel region. During an erase operation, a ground potential is applied to the drain and the source regions, and a high positive voltage is applied to the control gate. The positive charge on the control gate causes charges, if any, on the floating gate to be induced through the so-called Fowler-Nordheim tunneling mechanism to tunnel through the insulating layer 6 to the control gate, allowing the floating gate to be discharged.
To maximize the Fowler-Nordheim tunneling effect, sharp corners are formed at the edge of the float gate. The sharp comers are created by selectively forming poly oxide only in the floating gate region during one of the photolithographic processes implemented in fabricating the flash memory cell. FIGS. 2A and 2B show the longitudinal and transverse views, respective, of the memory cell during the fabrication process, wherein the poly oxide layer is formed on top of the floating gate, using the nitride layer as a mask. However primarily due to the stress exerted at the edge of the nitride layer, often defects in such oxide layer will be created near the sharp comer neighborhood of the floating gate, causing charges to be trapped in the oxide defects at the sharp comer and the resultant degradations in the erase efficiency. Erase failure is a major problem in cycling tests. And flash memory cells with defective poly oxide often shows poor cycling test results.
U.S. Pat. Nos. 5,045,488,5,067,1078,5,202850, and 5,278,087 disclose a single transistor electrically programmable and erasable memory cell having a second insulating layer with a top wall portion over the floating gate and a side wall portion immediately adjacent to the floating gate and has a thickness which permits the Fowler-Nordheim tunneling or charges therethrough. However, these patents never taught or suggested the existence of the defects in the oxide layer near the sharp corner neighborhood of the floating gate as mentioned above which can result in degradations in the erase efficiency of the memory cell.
The primary object of the present invention is to develop an improved split gate flash memory with reduced rate of erase failures. More specifically, the primary object of the present invention is to develop a method for making improved split gate flash memory cells having a high integrity oxide layer to ensure high erase efficiency, wherein the memory cell utilizes the poly1 (floating gate) to poly2 (control gate) Fowler-Nordheim channeling of charges through the sharp corner at the floating gate edge to achieve charge erase operation.
The improved split gate flash memory cells disclosed in the present invention prevent or at least minimize potential degradations of erase efficiency experienced from the prior art flash memory cells which occur due to charge trapping as a result of oxide defects which exist at the sharp corner at the edges of the floating gate. The method disclosed in the present invention also allows the size of the floating gate, thus the overall memory cell dimension, to be smaller than that typically achievable from the underlying photolithography technology. By doing so, the present invention allows scaling of the flash memory cells without incurring large expenses typically associated with equipment upgrade.
One of the key element of the present invention is to etch a reentrant angle during the floating gate etch and other associated steps, so as to ensure that a sharp angle is preserved at the corner of the floating gate. The present invention comprises the following main steps:
(1) Forming a floating gate having a width generally increasing with distance from the substrate by etching a reentrant angle during the floating gate etch;
(2) Forming a nitride spacer on the floating gate using a CVD nitride deposition and subsequent anisotropic etching of the CVD nitride;
(3) Forming a control gate on the floating gate to assume a split gate structure; and
(4) Source and Drain implantation.
Each of the main steps also comprises several sub-steps. These are discussed below:
(1) Forming a floating gate having a width generally increasing with distance from a substrate by etching a reentrant angle during the floating gate etch:
In this main step, a tunnel oxide layer is first formed on a substrate, followed by the deposition of poly1 layer and subsequent poly1 implantation. Then a poly oxide layer is formed on the poly1 layer. The thickness of the poly oxide layer should be adequate to reduce the coupling between the control gate and the floating tate that will be ultimately formed. Typically, the thickness of the poly oxide layer should be between about 1,000 and 3,000 xc3x85. A poly1 mask is employed to define the floating gate pattern. Finally, the stack of poly oxide and poly1 layers are etched under conditions to form a reentrant angle. The magnitude of the reentrant angle is a design parameter which should be the best compromise between erase efficiency and the step coverage of the oxide/nitride films to be subsequently formed. Typically a reentrant angle of aboutxc2x115xc2x0 should be adequate.
(2) Forming a nitride spacer on the floating gate using a CVD nitride deposition and anisotropic etching of the CVD nitride:
In this main step, an oxide layer of about 100 to 250 xc3x85 is deposited around the floating gate via a chemical vapor deposition (CVD) technique, followed by the CVD deposition of a nitride layer. These two insulation layers are called CVD oxide layer and CVD nitride layer, respectively. Finally, an anisotropic etch is applied on the CVD nitride to form a nitride spacer on the floating gate.
(3) Forming a control gate on the floating gate to assume a split gate structure; and
In main step (3), a poly2 layer is deposited on the substrate covering the floating gate and the associated oxide and nitride layers, followed by poly2 implantation and polycide formation. A poly2 mask is employed to define the control gate pattern. Finally, a poly2 etch is performed to form the control gate.
(4) Source and Drain implantation.
In this main step, a source implant mask is first applied, followed by a LATID (LArge Tilt-angle Implanted Drain) source implant with four way rotations. The LATID angle should preferably be close to the reentrant angle of poly1. Finally, the photoresist is removed and the source implant is annealed. Similar procedure is applied to achieve a drain implant.
The reentrant angle formed at the floating gate eliminates or at least minimizes the stress that the nitride may exert on the floating gate, thus eliminating or at least minimizing the possibility that defects may be formed in the poly oxide. As a result, failure rate during erase operations can be at least substantially reduced.